View ICS94206_81693.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

Integrated Circuit Systems, Inc.
ICS94206
Programmable System Frequency Generator for PII/IIITM
Recommended Application: 440BX - VIA Apollo Pro133 - ALI 1631 style chipset. Output Features: * 2 - CPUs @2.5V * 1 - IOAPIC @ 2.5V * 13 - SDRAM @ 3.3V * 6 - PCI @3.3V, * 1 - 48MHz, @3.3V * 1 - 24MHz @ 3.3V * 2 - REF @3.3V, 14.318MHz. Features: * Programmable ouput frequency. * Programmable ouput rise/fall time. * Programmable PCI_F and PCICLK skew. * Spread spectrum for EMI control typically by 7dB to 8dB, with programmable spread percentage. * Watchdog timer technology to reset system if over-clocking causes malfunction. * Uses external 14.318MHz crystal. * FS pins for frequency select Key Specifications: * CPU - CPU: <175ps * SDRAM - SDRAM: <500ps * PCI - PCI: <500ps * CPU(early)-PCI: Min=1.0ns, Typ=2.0ns, Max=4.0ns
Pin Configuration
VDD1 *PCI_STOP/REF0 GND X1 X2 VDD2 *MODE/PCICLK_F **FS3/PCICLK0 GND PCICLK1 PCICLK2 PCICLK3 PCICLK4 VDD2 BUFFER IN GND SDRAM11 SDRAM10 VDD3 SDRAM9 SDRAM8 GND SDATA SCLK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 VDDL1 IOAPIC REF1/FS2* GND CPUCLK_F CPUCLK1 VDDL2 CLK_STOP#* SDRAM_F GND SDRAM0 SDRAM1 VDD3 SDRAM2 SDRAM3 GND SDRAM4 SDRAM5 VDD3 SDRAM6 SDRAM7 VDD4 48MHz/FS0* 24MHz/FS1*
48-Pin 300mil SSOP
* Internal Pull-up Resistor of 120K to VDD ** Internal Pull-down resistor of 120K to GND
Functionality Block Diagram
PLL2 /2 X1 X2 BUFFER IN XTAL OSC 48MHz 24MHz IOAPIC REF(1:0) CPUCLK_F PLL1 Spread Spectrum FS(3:0) 4 MODE
STOP
ICS94206
FS3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
FS2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
FS1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
FS0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
STOP
2
CPUCLK 1
LATCH
STOP
12
SDRAM (11:0) SDRAM_F
4
POR
CLK_STOP# PCI_STOP# SDATA SCLK Control Logic Config. Reg.
PCI CLOCK DIVDER
STOP
5
PCICLK (4:0) PCICLKF
CPU (MHz) 80.00 75.00 83.31 66.82 103.00 112.01 68.01 100.23 120.00 114.99 109.99 105.00 140.00 150.00 124.00 132.99
PCICLK (MHz) 40.00 37.50 41.65 33.41 34.33 37.34 34.01 33.41 40.00 38.33 36.66 35.00 35.00 37.50 31.00 33.25
94206 Rev B 04/26/01
ICS reserves the right to make changes in the device data identified in this publication without further notice. ICS advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate.
ICS94206
General Description
The ICS94206 is a single chip clock solution for desktop designs using the BX/Apollo Pro133/ALI 1631 style chipset. It provides all necessary clock signals for such a system. The ICS94206 belongs to ICS new generation of programmable system clock generators. It employs serial programming I2C interface as a vehicle for changing output functions, changing output frequency, configuring output strength, configuring output to output skew, changing spread spectrum amount, changing group divider ratio and dis/enabling individual clocks. This device also has ICS propriety 'Watchdog Timer' technology which will reset the frequency to a safe setting if the system become unstable from over clocking.
Pin Configuration
PIN NUMBER 1 2 3,9,16,22, 33,39,45 4 5 6,14 7 MODE1, 2 FS3 8 13, 12, 11, 10 15 17, 18, 20, 21, 28, 29, 31, 32, 34, 35,37,38 19,30,36 23 24 25 26 27 40 41 42 43 44 46 47 48 PCICLK0 PCICLK(4:1) BUFFER IN SDRAM (11:0) VDD3 SDATA SCLK 24MHz FS11, 2 48MHz FS01, 2 VDD4 SDRAM_F CLK_STOP# VDDL2 CPUCLK1 CPUCLK_F REF1 FS21, 2 I OA P I C VDDL1 IN IN OUT OUT IN OUT PWR I/O IN OUT IN OUT IN PWR OUT IN PWR OUT OUT OUT IN OUT PWR P I N NA M E VDD1 REF0 PCI_STOP#1 GND X1 X2 VDD2 PCICLK_F TYPE DESCRIPTION P W R Ref, XTAL power supply, nominal 3.3V O U T 14.318 Mhz reference clock. Halts PCICLK clocks at logic 0 level, when input low (In mobile IN mode, MODE=0) PWR IN OUT PWR OUT Ground Crystal input, has internal load cap (36pF) and feedback resistor from X2 Crystal output, nominally 14.318MHz. Has internal load cap (36pF) Supply for PCICLK_F and PCICLK (0:4), nominal 3.3V Free running PCI clock not affected by PCI_STOP# for power management. Pin 7 function select pin, 1=Desktop Mode, 0=Mobile Mode. Latched Input. Frequency select pin. Latched Input. Internal Pull-down to GND PCI clock outputs. Syncheronous to CPU clocks with 1-48ns skew (CPU early) PCI clock outputs. Syncheronous to CPU clocks with 1-48ns skew (CPU early) Input to Fanout Buffers for SDRAM outputs. SDRAM clock outputs, Fanout Buffer outputs from BUFFER IN pin (controlled by chipset). Supply for SDRAM (0:12) and CPU PLL Core, nominal 3.3V. Data pin for I2C circuitry 5V tolerant Clock input of I2C input, 5V tolerant input 24MHz output clock Frequency select pin. Latched Input. 48MHz output clock Frequency select pin. Latched Input Power for 24 & 48MHz output buffers and fixed PLL core. Free running SDRAM clock output. Not affected by CPU_STOP# This asynchronous input halts CPUCLK1, IOAPIC & SDRAM (0:11) at logic "0" level when driven low. Supply for CPU clocks, either 2.5V or 3.3V nominal CPU clock outputs, powered by VDDL2. Low if CPU_STOP#=Low Free running CPU clock. Not affected by the CPU_STOP# 14.318 MHz reference clock. Frequency select pin. Latched Input IOAPIC c l o c k o u t p u t . 1 4 . 3 1 8 M H z P ow e r e d b y V D D L 1 . Supply for IOAPIC, either 2.5 or 3.3V nominal
Notes: 1: Internal Pull-up Resistor of 120K to 3.3V on indicated inputs 2: Bidirectional input/output pins, input logic levels are latched at internal power-on-reset. Use 10Kohm resistor to program logic Hi to VDD or GND for logic low.
2
ICS94206
General I2C serial interface information for the ICS94206 How to Write:
* * * * * * * * Controller (host) sends a start bit. Controller (host) sends the write address D2 (H) ICS clock will acknowledge Controller (host) sends a dummy command code ICS clock will acknowledge Controller (host) sends a dummy byte count ICS clock will acknowledge Controller (host) starts sending Byte 0 through Byte 20 (see Note) * ICS clock will acknowledge each byte one at a time * Controller (host) sends a Stop bit
How to Read:
Controller (host) will send start bit. Controller (host) sends the read address D3 (H) ICS clock will acknowledge ICS clock will send the byte count Controller (host) acknowledges ICS clock sends Byte 0 through byte 8 (default) ICS clock sends Byte 0 through byte X (if X(H) was written to byte 8). * Controller (host) will need to acknowledge each byte * Controller (host) will send a stop bit * * * * * * *
How to Write:
Controller (Host) Start Bit Address D2(H) Dummy Command Code ACK Dummy Byte Count ACK Byte 0 ACK Byte 1 ACK Byte 2 ACK Byte 3 ACK Byte 4 ACK Byte 5 ACK Byte 6 ACK ICS (Slave/Receiver)
How to Read:
Controller (Host) Start Bit Address D3(H) ICS (Slave/Receiver)
ACK
ACK Byte Count ACK Byte 0 ACK Byte 1 ACK Byte 2 ACK Byte 3 ACK Byte 4 ACK Byte 5 ACK Byte 6 ACK If 7H has been written to B6 ACK Byte 7
Byte 18 ACK Byte 19 ACK Byte 20 ACK Stop Bit
*See notes on the following page.
If 12H has been written to B6 ACK If 13H has been written to B6 ACK If 14H has been written to B6 ACK Stop Bit
Byte18 Byte 19 Byte 20
3
ICS94206
Brief I2C registers description for ICS94206 Programmable System Frequency Generator
Register Name Functionality & Frequency Select Register Output Control Registers Byte 0 Description Output frequency, hardware / I C frequency select, spread spectrum & output enable control register. Active / inactive output control registers/latch inputs read back. Byte 11 bit[7:4] is ICS vendor id - 1001. Other bits in this register designate device revision ID of this part. Writing to this register will configure byte count and how many byte will be read back. Do not write 00 H to this byte. Writing to this register will configure the number of seconds for the watchdog timer to reset. Watchdog enable, watchdog status and programmable 'safe' frequency' can be configured in this register. This bit select whether the output frequency is control by hardware/byte 0 configurations or byte 11&12 programming. These registers control the dividers ratio into the phase detector and thus control the VCO output frequency. These registers control the spread percentage amount. Increment or decrement the group skew amount as compared to the initial skew. These registers will control the output rise and fall time.
2
PWD Default See individual byte description See individual byte description See individual byte description
1-6
Vendor ID & Revision ID Registers
7
Byte Count Read Back Register
8
08 H
Watchdog Timer Count Register
9
10 H
Watchdog Control Registers 10 Bit [6:0]
000,0000
VCO Control Selection Bit
10 Bit [7]
0
VCO Frequency Control Registers Spread Spectrum Control Registers Group Skews Control Registers Output Rise/Fall Time Select Registers
11-12
Depended on hardware/byte 0 configuration Depended on hardware/byte 0 configuration See individual byte description See individual byte description
13-14
15-16 17-20
Notes:
1. The ICS clock generator is a slave/receiver, I2C component. It can read back the data stored in the latches for verification. Readback will support standard SMBUS controller protocol. The number of bytes to readback is defined by writing to byte 8. When writing to byte 11 - 12, and byte 13 - 14, they must be written as a set. If for example, only byte 14 is written but not 15, neither byte 14 or 15 will load into the receiver. The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode) The input is operating at 3.3V logic levels. The data byte format is 8 bit bytes. To simplify the clock generator I2C interface, the protocol is set to use only Block-Writes from the controller. The bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte has been transferred. The Command code and Byte count shown above must be sent, but the data is ignored for those two bytes. The data is loaded until a Stop sequence is issued. At power-on, all registers are set to a default condition, as shown.
2. 3. 4. 5. 6.
7.
4
ICS94206
Byte 0: Functionality and frequency select register (Default=0)
Bit Bit2
Description PCICLK CPUCLK MHz MHz FS3 FS2 FS1 FS0 0 0 0 0 0 80.00 40.00 0 0 0 0 1 75.00 37.50 0 0 0 1 0 83.31 41.65 0 0 0 1 1 66.82 33.41 0 0 1 0 0 103.00 34.33 0 0 1 0 1 112.01 37.34 0 0 1 1 0 68.01 34.01 0 0 1 1 1 100.23 33.41 0 1 0 0 0 120.00 40.00 0 1 0 0 1 114.99 38.33 0 1 0 1 0 109.99 36.66 0 1 0 1 1 105.00 35.00 0 1 1 0 0 140.00 35.00 0 1 1 0 1 150.00 37.50 0 1 1 1 0 124.00 31.00 0 1 1 1 1 132.99 33.25 1 0 0 0 0 135.00 33.75 1 0 0 0 1 129.99 32.50 1 0 0 1 0 126.00 31.50 1 0 0 1 1 118.00 39.33 1 0 1 0 0 115.98 38.66 1 0 1 0 1 95.00 31.67 1 0 1 1 0 90.00 30.00 1 0 1 1 1 85.01 28.34 1 1 0 0 0 166.00 41.50 1 1 0 0 1 160.01 40.00 1 1 0 1 0 154.99 38.75 1 1 0 1 1 147.95 36.99 1 1 1 0 0 145.98 36.50 1 1 1 0 1 143.98 35.99 1 1 1 1 0 141.99 35.50 1 1 1 1 1 138.01 34.50 0-Frequency is selected by hardware select, latched inputs 1- Frequency is selected by Bit 2,7:4 0- Normal 1- Spread spectrum enable 0.35% Center Spread 0- Running 1- Tristate all outputs Bit7 Bit6 Bit5 Bit4
PWD
Bit (2,7:4)
Note 1
Bit 3 Bit 1 Bit 0
0 1 0
Notes: 1. Default at power-up will be for latched logic inputs to define frequency, as displayed by Bit 3.
5
ICS94206
Byte 1: CPU, Active/Inactive Register (1= enable, 0 = disable)
Byte 2: PCI, Active/Inactive Register (1= enable, 0 = disable)
BIT
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
PIN#
40 43 44
PWD
X 1 1 1 1 1 1 1
DESCRIPTION
Latched FS2# (Reserved) (Reserved) (Reserved) SDRAM_F (Reserved) CPUCLK1 CPUCLK_F
BIT
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
PIN#
7 13 12 11 10 8
PWD
1 1 1 1 1 1 1 1
DESCRIPTION
(Reserved) PCICLK_F (Reserved) PCICLK4 PCICLK3 PCICLK2 PCICLK1 PCICLK0
Byte 3: SDRAM, Active/Inactive Register (1= enable, 0 = disable)
Byte 4: Reserved , Active/Inactive Register (1= enable, 0 = disable)
BIT
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
PIN#
26 25 21,20,18,17 32,31,29,28 38,37,35,34
PWD
1 X 1 1 1 1 1 1
DESCRIPTION
(Reserved) Latched FS0# 48MHz 24 MHz (Reserved) SDRAM (8:11) SDRAM (4:7) SDRAM (0:3)
BIT
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
PIN# PWD
1 1 1 1 X 1 X 1
DESCRIPTION
(Reserved) (Reserved) (Reserved) (Reserved) Latched FS1# (Reserved) Latched FS3# (Reserved)
Byte 5: Peripheral , Active/Inactive Register (1= enable, 0 = disable)
Byte 6: Peripheral , Active/Inactive Register (1= enable, 0 = disable)
BIT
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Notes:
PIN# PWD
47 46 2 1 1 1 1 1 1 1 1
DESCRIPTION
(Reserved) (Reserved) (Reserved) IOAPIC0 (Reserved) (Reserved) REF1 REF0
BIT Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
PIN# -
PWD 0 0 0 0 0 1 1 0
DESCRIPTION R e s e r ve d ( N o t e ) R e s e r ve d ( N o t e ) R e s e r ve d ( N o t e ) R e s e r ve d ( N o t e ) R e s e r ve d ( N o t e ) R e s e r ve d ( N o t e ) R e s e r ve d ( N o t e ) R e s e r ve d ( N o t e )
1. Inactive means outputs are held LOW and are disabled from switching. 2. Latched Frequency Selects (FS#) will be inverted logic load of the input frequency select pin conditions.
Note: This is an unused register writing to this register will not affect device performance or functinality.
6
ICS94206
Byte 7: Vendor ID and Revision ID Register
Byte 8: Byte Count and Read Back Register
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
PWD 0 0 1 X X X X X
Description Vendor ID Vendor ID Vendor ID Revision ID Revision ID Revision ID Revision ID Revision ID
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
PWD 0 0 0 0 1 0 0 0
Description Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
Byte 9: VCO Control Selection Bit & Watchdog Timer Control Register
Byte 10: Watchdog Timer Count Register
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
PWD 0 0 0 0 0 0 0 0
Description 0=Hw/B0 freq / 1=B14&15 freq WD Enable 0=disable / 1=enable WD Status 0=normal / 1=alarm WD Safe Frequency, Byte 0 bit 2 WD Safe Frequency, FS3 WD Safe Frequency, FS2 WD Safe Frequency, FS1 WD Safe Frequency, FS0
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
PWD 0 0 0 1 0 0 0 0
Description The decimal representation of these 8 bits correspond to 290ms or 1ms the watchdog timer will wait before it goes to alarm mode and reset the frequency to the safe setting. Default at power up is 16X 290ms = 4.6 seconds.
Note: FS values in bit [0:4] will correspond to Byte 0 FS values. Default safe frequency is same as 00000 entry in byte0.
Byte 11: VCO Frequency Control Register
Byte 12: VCO Frequency Control Register
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
PWD X X X X X X X X
Description VCO Divider Bit0 REF Divider Bit6 REF Divider Bit5 REF Divider Bit4 REF Divider Bit3 REF Divider Bit2 REF Divider Bit1 REF Divider Bit0
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
PWD X X X X X X X X
Description VCO Divider Bit8 VCO Divider Bit7 VCO Divider Bit6 VCO Divider Bit5 VCO Divider Bit4 VCO Divider Bit3 VCO Divider Bit2 VCO Divider Bit1
Note: The decimal representation of these 7 bits (Byte 11 [6:0]) + 2 is equal to the REF divider value .
Notes: 1. PWD = Power on Default
Note: The decimal representation of these 9 bits (Byte 12 bit [7:0] & Byte 11 bit [7] ) + 8 is equal to the VCO divider value. For example if VCO divider value of 36 is desired, user need to program 36 - 8 = 28, namely, 0, 00011100 into byte 12 bit & byte 11 bit 7.
7
ICS94206
Byte 13: Spread Sectrum Control Register
Byte 14: Spread Sectrum Control Register
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
PWD X X X X X X X X
Description Spread Spectrum Bit7 Spread Spectrum Bit6 Spread Spectrum Bit5 Spread Spectrum Bit4 Spread Spectrum Bit3 Spread Spectrum Bit2 Spread Spectrum Bit1 Spread Spectrum Bit0
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
PWD X X X X X X X X
Description Reserved Reserved Reserved Spread Spectrum Bit12 Spread Spectrum Bit11 Spread Spectrum Bit10 Spread Spectrum Bi 9 Spread Spectrum Bit8
Note: Please utilize software utility provided by ICS Application Engineering to configure spread spectrum. Incorrect spread percentage may cause system failure.
Note: Please utilize software utility provided by ICS Application Engineering to configure spread spectrum. Incorrect spread percentage may cause system failure.
Byte 15: Output Skew Control
Byte 16: Output Skew Control
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
PWD
Description PCI_F Skew Control PCICLK [0:4} Skew Control SDRAM_F Skew Control SDRAM [0:7} Skew Control
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
PWD
Description SDRAM [8:11] Skew Control
X X X X X X
Reserved Reserved Reserved Reserved Reserved Reserved
Byte 17: Output Rise/Fall Time Select Register
Byte 18: Output Rise/Fall Time Select Register
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
PWD
Description CPUCLK_F: Slew Rate Control CPUCLK1: Slew Rate Control SDRAM_F: Slew Rate Control SDRAM [0:11] Slew Rate Control
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
PWD
Description PCI {0:4]: Slew Rate Control PCI_F Slew Rate Control 48MHz: Slew Rate Control 24MHz: Slew Rate Control
Notes: 1. PWD = Power on Default 2. The power on default for byte 13-20 depends on the harware (latch inputs FS[0:4]) or I2C (Byte 0 bit [1:7]) setting. Be sure to read back and re-write the values of these 8 registers when VCO frequency change is desired for the first pass. 3. If Byte 8 bit 7 is driven to "1" meaning programming is intended, Byte 21-24 will lose their default power up value.
8
ICS94206
Byte 19: Reserved Register Byte 20: Reserved Register
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
PWD X X X X X X X X
Description Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
PWD X X X X X X X X
Description Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
Note: Byte 19 and 20 are reserved registers, these are
unused registers writing to these registers will not affect device performance or functinality.
VCO Programming Constrains VCO Frequency ...................... 150MHz to 500MHz VCO Divider Range ................ 8 to 519 REF Divider Range ................. 2 to 129 Phase Detector Stability .......... 0.3536 to 1.4142 Useful Formula VCO Frequency = 14.31818 x VCO/REF divider value Phase Detector Stabiliy = 14.038 x (VCO divider value)-0.5 To program the VCO frequency for over-clocking. 0. Before trying to program our clock manually, consider using ICS provided software utilities for easy programming. 1. Select the frequency you want to over-clock from with the desire gear ratio (i.e. CPU:SDRAM:3V66:PCI ratio) by writing to byte 0, or using initial hardware power up frequency. 2. Write 0001, 1001 (19H) to byte 8 for readback of 21 bytes (byte 0-20). 3. Read back byte 11-20 and copy values in these registers. 4. Re-initialize the write sequence. 5. Write a '1' to byte 9 bit 7 and write to byte 11 & 12 with the desired VCO & REF divider values. 6. Write to byte 13 to 20 with the values you copy from step 3. This maintains the output spread, skew and slew rate. 7. The above procedure is only needed when changing the VCO for the 1st pass. If VCO frequency needed to be changed again, user only needs to write to byte 11 and 12 unless the system is to reboot. Note: 1. User needs to ensure step 3 & 7 is carried out. Systems with wrong spread percentage and/or group to group skew relation programmed into bytes 13-16 could be unstable. Step 3 & 7 assure the correct spread and skew relationship. 2. If VCO, REF divider values or phase detector stability are out of range, the device may fail to function correctly. 3. Follow min and max VCO frequency range provided. Internal PLL could be unstable if VCO frequency is too fast or too slow. Use 14.31818MHz x VCO/REF divider values to calculate the VCO frequency (MHz). 4. ICS recommends users, to utilize the software utility provided by ICS Application Engineering to program the VCO frequency. 5. Spread percent needs to be calculated based on VCO frequency, spread modulation frequency and spreadamount desired. See Application note for software support. 9
ICS94206
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ambient Operating Temperature . . . . . . . . . . . . . . Case Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . 7.0 V GND -0.5 V to VDD +0.5 V 0C to +70C 115C -65C to +150C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70C; Supply Voltage VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5% (unless otherwise stated) PARAMETER SYMBOL CONDITIONS MIN TYP Input High Voltage VIH 2 Input Low Voltage VIL VSS-0.3 Input High Current IIH VIN = VDD -5 IIL1 VIN = 0 V; Inputs with no pull-up resistors -5 Input Low Current IIL2 VIN = 0 V; Inputs with pull-up resistors -200 CL = max cap loads; 124 IDD3.3OP Operating Supply CPU=66-133 MHz, SDRAM=100 MHz CPU=133 MHz, SDRAM=133 MHz 135 Current CL = max cap loads; IDD2.5OP 18 IDD3.3PD CL = 0 pF; Input address to VDD or GND Powerdown Current VDD = 3.3 V 14.318 Input Frequency Fi Pin Inductance Lpin CIN Logic Inputs COUT Output pin capacitance Input Capacitance1 CINX X1 & X2 pins 27 Transition time1 Settling time Clk Stabilization1 Delay1
1
MAX VDD+0.3 0.8 5
UNITS V V A A
350 500 70 600 7 5 6 45 3 3 3 10 10 mA A MHz nH pF pF pF ms ms ms ns ns
Ttrans Ts TSTAB tPZH,tPZL tPHZ,tPLZ
To 1st crossing of target frequency From 1st crossing to 1% target frequency From VDD = 3.3 V to 1% target frequency Output enable delay (all outputs) Output disable delay (all outputs) 1 1
Skew
1
1
tcpu-pci
VT = 1.5V; VTL=1.25V
2.45
4
ns
Guaranteed by design, not 100% tested in production.
10
ICS94206
Electrical Characteristics - CPU
TA = 0 - 70 C;VDD = 3.3V; VDDL = 2.5 V +/-5%; CL = 10 - 20 pF (unless otherwise stated) PARAMETER SYMBOL CONDITIONS MIN 1 Output Impedance RDSP2B Vo=VDD*(0.5) 13.5 1 Output Impedance RDSN2B Vo=VDD*(0.5) 13.5 IOH = -1 mA 2 Output High Voltage VOH2B Output Low Voltage VOL2B IOL = 1 mA VOH@MIN = 1 V IOH2B Output High Current -27 VOH@MAX = 2.375V VOL@MIN = 1.2 V 27 IOL2B Output Low Current VOL@MAX =0.3V 1 Rise Time tr2B VOL = 0.4 V, VOH = 2.0 V 0.4 1 Fall Time tf2B VOH = 2.0 V, VOL = 0.4 V 0.4 1 Duty Cycle dt2B VT = 1.25 V 45 1 Skew tsk2B VT = 1.25 V tjcyc-cyc2B VT = 1.25 V, CPU 66, SDRAM 100 Jitter, Cycle-to-cycle1
1
TYP 15 16.5 2.48 0.04 -60 -7 63 20 1.2 0.9 46.9 12.7 150
MAX UNITS 45 45 V 0.4 V -27 mA mA ns ns % ps ps
30 1.6 1.6 55 175 250
Guaranteed by design, not 100% tested in production.
Electrical Characteristics - PCI
TA = 0 - 70 C; VDD = 3.3 V +/-5%, CL = 40 pF for PCI0-1, CL = 10 - 30 pF for other PCIs (unless otherwise stated) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS 1 Output Impedance RDSP1 Vo=VDD*(0.5) 12 55 1 Output Impedance RDSN1 Vo=VDD*(0.5) 12 55 Output High Voltage VOH1 IOH = -1 mA 2.4 V Output Low Voltage VOL1 IOL = 1 mA 0.55 V VOH@MIN = 1 V -33 IOH1 Output High Current mA VOH@MAX = 3.135V -33 VOL@MIN = 1.95 V 30 IOL1 Output Low Current mA VOL@MAX =0.4V 38 tr1 0.5 ns VOL = 0.4 V, VOH = 2.4 V, 1.5 2 Rise Time1 Fall Time
1 1 1
tf1 dt1 tsk1 tjcyc-cyc1
VOL = 2.4 V, VOH = 0.4 V, PCI0-3 VT = 1.5 V VT = 1.5 V VT = 1.5 V
0.5 45
1.5 52.5 49 200
2 55 500 500
ns % ps ps
Duty Cycle
Skew Jitter, cycle-to-cycle1
1
Guaranteed by design, not 100% tested in production.
11
ICS94206
Electrical Characteristics - SDRAM
TA = 0 - 70 C; VDD = 3.3 V +/-5%, CL = 20 - 30 pF (unless otherwise stated) PARAMETER SYMBOL CONDITIONS 1 Output Impedance RDSP3 Vo=VDD*(0.5) Output Impedance1 RDSN3 Vo=VDD*(0.5) IOH = -1 mA Output High Voltage VOH3 IOL = 1 mA Output Low Voltage VOL3 VOH@MIN = 2 V IOH3 Output High Current VOH@MAX = 3.135V VOL@MIN = 1 V IOL3 Output Low Current VOL@MAX =0.4V Rise Time Fall Time
1 1
MIN 10 10 2.4
TYP
-54 54 0.4 0.4 45 0.8 0.8 51.7 166 3.1
MAX UNITS 24 24 V 0.4 V -46 mA mA ns ns % ps ns
53 1.6 1.6 55 250 5
tr3 tf3 dt3 tsk3 Tprop
VOL = 0.4 V, VOH = 2.4 V VOH = 2.4 V, VOL = 0.4 V VT = 1.5 V VT = 1.5 V VT = 1.5 V
1 1
Duty Cycle
Skew Propagation Delay
1
Guaranteed by design, not 100% tested in production.
Electrical Characteristics - IOAPIC
TA = 0 - 70 C; VDD = 3.3V; VDDL = 2.5 V +/-5%; CL = 10 - 20 pF (unless otherwise stated) PARAMETER SYMBOL CONDITIONS MIN 1 Output Impedance 9 RDSP4B Vo=VDD*(0.5) 1 Output Impedance 9 RDSN4B Vo=VDD*(0.5) IOH = -5.5 mA 2 Output High Voltage VOH4B IOL = 9 mA Output Low Voltage VOL4B VOH@MIN = 1.4 V IOH4B Output High Current -36 VOH@MAX = 2.5V 36 VOL@MIN = 1.0 V IOL4B Output Low Current VOL@MAX =0.2V Rise Time1 Fall Time Duty Cycle1
1 1
TYP
MAX UNITS 3 30 V 0.4 V -21 mA mA ns ns %
31 0.7 1.1 53.7 1.6 1.6 55
tr4B tf4B dt4B
VOL = 0.4 V, VOH = 2.0 V VOH = 2.0 V, VOL = 0.4 V VT = 1.25 V
0.4 0.4 45
Guaranteed by design, not 100% tested in production.
12
ICS94206
Electrical Characteristics - REF, 24_48MHz, 48MHz
T A = 0 - 70C; VDD = 3.3 V +/-5%; CL = 10-20 pF (unless otherwise specified) PARAMETER SYMBOL CONDITIONS 1 Output Impedance RDSP5 VO = VDD*(0.5) 1 Output Impedance RDSN5 VO = VDD*(0.5) Output High Voltage VOH5 IOH = -1 mA Output Low Voltage VOL5 IOL = 1 mA VOH @ MIN = 1.0 V IOH5 Output High Current VOH @ MAX = 3.135 V VOL @ MIN = 1.95 V IOL5 Output Low Current VOL @ MAX = 0.4 V Rise Time Fall Time
1
MIN 20 20 2.4
TYP
-29 29 0.4 0.4 45 2 2 53 200 1032
MAX UNITS 60 60 V 0.4 V -23 mA mA ns ns % ps
27 4 4 55 500 1250
tr5 tf5 dt5
1
VOL = 0.4 V, VOH = 2.4 V VOH = 2.4 V, VOL = 0.4 V VT = 1.5 V VT = 1.5 V, Fixed clocks VT = 1.5 V, Ref clocks
1 1
Duty Cycle
Jitter, cycle-to-cycle
1
tjcyc-cyc5
Guaranteed by design, not 100% tested in production.
13
ICS94206
Shared Pin Operation Input/Output Pins
The I/O pins designated by (input/output) on the ICS94206 serve as dual signal functions to the device. During initial power-up, they act as input pins. The logic level (voltage) that is present on these pins at this time is read and stored into a 5bit internal data latch. At the end of Power-On reset, (see AC characteristics for timing values), the device changes the mode of operations for these pins to an output function. In this mode the pins produce the specified buffered clocks to external loads. To program (load) the internal configuration register for these pins, a resistor is connected to either the VDD (logic 1) power supply or the GND (logic 0) voltage potential. A 10 Kilohm (10K) resistor is used to provide both the solid CMOS programming voltage needed during the power-up programming period and to provide an insignificant load on the output clock during the subsequent operating period. Figure 1 shows a means of implementing this function when a switch or 2 pin header is used. With no jumper is installed the pin will be pulled high. With the jumper in place the pin will be pulled low. If programmability is not necessary, than only a single resistor is necessary. The programming resistors should be located close to the series termination resistor to minimize the current loop area. It is more important to locate the series termination resistor close to the driver than the programming resistor.
Programming Header Via to Gnd Device Pad 2K W
Via to VDD
8.2K W Clock trace to load Series Term. Res.
Fig. 1
14
ICS94206
CLK_STOP# Timing Diagram
CLK_STOP# is an asychronous input to the clock synthesizer. It is used to turn off the CPU clocks for low power operation. CLK_STOP# is synchronized by the ICS94206. The minimum that the CPU clock is enabled (CLK_STOP# high pulse) is 100 CPU clocks. All other clocks will continue to run while the CPU clocks are disabled. The CPU clocks will always be stopped in a low state and start in such a manner that guarantees the high pulse width is a full pulse. CPU clock on latency is less than 4 CPU clocks and CPU clock off latency is less than 4 CPU clocks.
INTERNAL CPUCLK PCICLK CLK_STOP# PCI_STOP# (High) IOAPIC
SDRAM CPUCLK CPUCLK _F SDRAM_F
Notes: 1. All timing is referenced to the internal CPU clock. 2. CLK_STOP# is an asynchronous input and metastable conditions may exist. This signal is synchronized to the CPU clocks inside the ICS94206. 3. IOAPIC output is Stopped Glitch Free by CLK_STOP# going low. 4. SDRAM-F output is controlled by Buffer in signal, not affected by the ICS94206 CLK_STOP# signal. SDRAM's are controlled as shown. 5. All other clocks continue to run undisturbed.
15
ICS94206
PCI_STOP# Timing Diagram
PCI_STOP# is an asynchronous input to the ICS94206. It is used to turn off the PCICLK clocks for low power operation. PCI_STOP# is synchronized by the ICS94206 internally. The minimum that the PCICLK clocks are enabled (PCI_STOP# high pulse) is at least 10 PCICLK clocks. PCICLK clocks are stopped in a low state and started with a full high pulse width guaranteed. PCICLK clock on latency cycles are only one rising PCICLK clock off latency is one PCICLK clock.
Notes: 1. All timing is referenced to the Internal CPUCLK (defined as inside the ICS94206 device.) 2. PCI_STOP# is an asynchronous input, and metastable conditions may exist. This signal is required to be synchronized inside the ICS94206. 3. All other clocks continue to run undisturbed. 4. CPU_STOP# is shown in a high (true) state.
16
ICS94206
0ns
10ns
20ns
30ns
40ns
Cycle Repeats
CPU 66MHz CPU 100MHz CPU 133MHz
SDRAM 100MHz SDRAM 133MHz
3.5V 66MHz PCI 33MHz APIC 33MHz REF 14.318MHz USB 48MHz
Group Offset Waveforms
17
ICS94206
N
c
L
SYMBOL A A1 b c D E E1 e h L N
INDEX AREA
E1
E
12 D h x 45
a
A A1
In Millimeters COMMON DIMENSIONS MIN MAX 2.41 2.80 0.20 0.40 0.20 0.34 0.13 0.25 SEE VARIATIONS 10.03 10.68 7.40 7.60 0.635 BASIC 0.38 0.64 0.50 1.02 SEE VARIATIONS 0 8 VARIATIONS D mm. MIN MAX 15.75 16.00
In Inches COMMON DIMENSIONS MIN MAX .095 .110 .008 .016 .008 .0135 .005 .010 SEE VARIATIONS .395 .420 .291 .299 0.025 BASIC .015 .025 .020 .040 SEE VARIATIONS 0 8
-Ce
b SEATING PLANE .10 (.004) C
N 48
10-0034
D (inch) MIN .620 MAX .630
Reference Doc.: JEDEC Publication 95, MO-118
300 mil SSOP Package
Ordering Information
ICS94206yF-T
Example:
ICS XXXX y F - T
Designation for tape and reel packaging Package Type F=SSOP
Revision Designator (will not correlate with datasheet revision)
Device Type Prefix ICS, AV = Standard Device
ICS reserves the right to make changes in the device data identified in this publication without further notice. ICS advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate.
18

▲Up To Search▲

Price & Availability of ICS94206

	To Download ICS94206 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .